`timescale 1ns/1ns
module add_4(
           input [3: 0] A,
           input [3: 0] B,
           input Ci,

           output wire [3: 0] S,
           output wire Co
       );
wire [3: 0] ci;

genvar i;
generate
	for (i = 0;i <= 3 ;i = i + 1 )
		begin:add
			add_full add_full(
			             .A ( A[i] ),
			             .B ( B[i] ),
			             .Ci ( i == 0 ? Ci : ci[i - 1] ),
			             .S ( S[i] ),
			             .Co ( ci[i] )
			         );

		end
endgenerate


assign Co = ci[3];
endmodule
